The present invention relates to integrated circuits and, more particularly, to output structures for CMOS integrated circuits. A major objective of the present invention is to enhance the resistance of dense CMOS integrated circuits to electrostatic discharge.
Much of modern progress is associated with the increasing circuit density and speeds of integrated circuits. Integrated circuits rely heavily on transistors as their primary functional units. CMOS (Complementary Metal-Oxide-Silicon) transistors use complementary NMOS and PMOS field-effect transistors in tandem to minimize power requirements and, accordingly, heat generation. Heat generation becomes an increasingly serious problem for dense integrated circuits since local heat accumulation can damage the circuit. CMOS technology provides for denser integrated circuits by minimizing this heat accumulation. Furthermore, the low CMOS power requirements are attractive for portable applications and, more generally, for energy conservation.
Each field-effect transistor includes a source, a drain, a channel, and a gate. The voltage at the gate controls the conductivity of the channel and thus controls the current between the source and the drain. Most commonly, the source, drain, and channel, are defined in a monocrytalline silicon substrate. In the case of NMOS transistors, the source and the drain are heavily doped with n-type dopant so that electrons are the majority carriers. In the case of PMOS transistors, the source and the drain are heavily doped to p-type dopant so that holes (absent electrons) are the majority carriers. Typically, the gate is of heavility doped polycrystalline silicon and is electrically insulated from the channel by a silicon dioxide "gate oxide" layer.
Each increase in circuit density is made possible by reductions in the minimum dimensions with which transistor elements can be defined. Circuit density is typically indicated by the design source-to-drain channel length. Early integrated circuits had dimensions measured in multiple microns. More recently submicron technologies have been developed to the point where commercial integrated circuits are being made with channel lengths well below 0.5 microns. Typically, most length and width dimensions scale roughly proportionally to channel length; thicknesses also tend to scale, but less proportionally.
As their dimensions fall, transistors become more affected by unintended electrical phenomena such as ESD, the hot-electron effect, and punch-through. The most notorious of these unintended electrical phenomena is electron-static discharge (ESD). ESD arises as accumulated charge jumps from one object to another, causing dielectric or junction breakdown. Lightning is a dramatic instance of ESD, but many people are familiar with it as the sparks that are generated when reaching for a metal object after shuffling across a carpet. Even in its more mundane form, ESD can wreak havoc on the tiny circuit elements of an integrated circuit. In fact, an ESD can cause the gate oxide to break down, destroying the integrated circuit.
ESD damage is best avoided by taking precautions against charge buildup in the vicinity of an integrated circuit. Systems incorporating integrated circuits must include proper grounding. People handling integrated circuit are cautioned to ground themselves (for example, using conductive wrist straps coupled to electrical ground). Despite these precautions, ESD can and does affect integrated circuits. Accordingly, integrated circuits are designed with ESD resistance as an objective.
During an ESD event, a transistor suffers a large drain voltage. If this voltage exceeds a first breakdown voltage (V.sub.t1) for the transistor, a drain current will flow. While the transistor is not functioning as intended during this breakdown, it can still resume normal operation once the ESD event is over. As soon as the current begins flowing, the drain voltage drops. However, if the ESD event is severe enough a second breakdown voltage V.sub.t2 is crossed, at which point the transistor is destroyed.
The primary approach to ESD resistance is to provide a large area for the breakdown current to flow. This slows the excursion to V.sub.t2, which in many cases can mean that the device escapes destruction. The large area can be provided by using larger transistors or multiple transistors in parallel or both. A problem with this approach to ESD resistance is that it runs counter to the general objective of higher density integrated circuits. In practice it can be implemented by applying it to only the most vulnerable transistors.
An integrated circuit can be divided conceptually between core transistors and input/output (I/O) transistors. The core transistors implement the logical design for the circuit, while the I/O transistors manage communications with the incorporating system. Since ESD usually arises from external sources, it is the I/O transistors that most need protection rather than the relatively numerous core transistors. Thus, relatively large and redundant I/O transistors can be used to provide ESD resistance without having a major impact on circuit density.
Not all unintended electric events are externally generated. There is a "hot-electron" effect in which electron hole pairs are generated due to the electric field in the section of the channel near the drain. If this electric field is strong enough, the electrons can inject into the neighboring gate oxide. The hot-electron effect causes the performance of a transistor to degrade over time. This degradation can cause a transistor to fall below specification around which a circuit was designed, causing the circuit to fail.
As device dimensions fell below one micron, the hot-electron effect became a more serious concern. It was dealt with using a lightly-doped drain (LDD) approach in which a lightly doped drain section separates the channel from a heavily doped drain section. This yielded a weaker field at the channel, reducing the likelihood that electrons would inject into the oxide.
Lightly doped drains could be formed as follows. After the gate polysilicon is patterned. A shallow light source/drain implant is made. Oxide sidewalls are then formed on the gates and a deep heavy implant is performed. The heavy doping defines the heavily-doped drain section. The lightly doped background extends beyond the heavily doped drain section to define a lightly doped drain section. Incidentally, the source is also divided into lightly and heavily doped sections. For a CMOS integrated circuit, this procedure is duplicated so that both LDD PMOS and LDD NMOS transistors are formed.
"Punch-through" is an unintended electrical effect that becomes serious when transistor dimensions fall below 0.5 microns. In punch-through, current can flow from source to drain irrespective of the gate voltage. Instead of flowing near the gate oxide, as does the normal source/drain current when the appropriate gate voltage is applied, the punch-through current tends to flow at a deeper level within the channel region.
Punch-through can be inhibited by counter-doping the channel region at the level at which punch-through could occur. A punch-through implant can be formed in several ways. One approach is to implant dopant across the entire channel region at a suitable depth. Such an implant can be performed before the gates are defined. Alternatively, punch-through implants can be performed at about the same stage as the lightly doped drain implants, e.g., after the gates are defined but before sidewalls are formed. In this latter case, the punch-through implant takes the form of counterdoped "pockets" adjacent the sources and drains.
The implants for the punch-through pockets must extend further under the gate than the lightly doped drains. This is not a problem for the NMOS transistors since the p-type dopant, typically boron, used to form the NMOS pockets is much more mobile than the n-type dopant, typically arsenic, used to form the lightly doped drain. The relative mobilities do not work out well for the PMOS transistors. Accordingly, a wide angle implant is used for the n-type pocket dopant so that more of it is implanted under the gate.
While there have been successful approaches to minimizing the harm due to the described unintended electrical effects, the problems they cause are far from being solved. Solutions that are effective at one stage in the development of integrated circuit technology can be strained with further reductions in feature dimensions. This is particularly true of ESD protection, which is weakened as smaller device dimensions require thinner gate oxides. Accordingly, there is still a need for an approach to providing better ESD protection for integrated circuits designed with dimensions below 0.5 microns.